1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates and, more particularly relates to via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof.
2. Description of the Related Art
The Complementary Metal Oxide Semiconductor (CMOS) technology has been recognized as the leading technology for use in digital electronics in general and for use in many computer products in particular. The miniaturization of CMOS technology according to a scaling rule is used in a semiconductor device to achieve large-scale integration and high-speed operation. In order to miniaturize CMOS devices, dual damascene technology has been applied to enhance integrity and speed of CMOS devices.
Generally, dual damascene technology includes: a via-first dual damascene process or a trench-first dual damascene process. For the via-first process, a via hole is first formed in a dielectric layer and on an etch stop layer covering a metal layer, and then a process for forming a trench is applied so as to form a via hole and trench structure. A conductive layer then is filled into the via hole and trench structure. A dual damascene structure is thus finished. In contrast, the trench-first process forms a trench in a dielectric layer, and then a process for defining a via hole is applied. No matter what process is applied, for connecting the metal layer with the conductive layer, the etch stop layer is penetrated.
FIGS. 1A and 1B are schematic cross sectional drawings showing a prior art method for removing a portion of an etch stop layer.
Referring to FIG. 1A, a metal layer 110 is in a substrate 100; an etch stop layer 120 covers the metal layer 110. A dielectric layer 130 is formed on the etch stop layer 120. A via hole and trench structure 140 is formed in the dielectric layer 130. As described above, the via hole and trench structure 140 can be formed by either a via-first process or a trench-first process. After the via hole and trench structure 140 is formed, the etch stop layer 120 still covers the metal layer 110. Before the formation of a conductive layer in the via hole and trench structure 140, an etch process 150 is applied to remove the etch stop layer 120 which is not covered by the dielectric layer 130.
Referring to FIG. 1B, an exposed top surface 110a of the metal layer 110 is formed in the via hole and trench structure 140. A problem occurs while the etch stop layer 120 which is not covered by the dielectric layer 130 is being removed. For the formation of the dual damascene structure, low-dielectric-constant materials have been adopted as the dielectric layer 130 for reducing intra-layer or inter-layer parasitic capacitances. Though having the advantage of low dielectric constants, these materials are vulnerable to the etch process 150 that includes a plasma treatment. After the plasma treatment, the physical structure and the inherent properties of the dielectric layer 130 are changed. Due to the change of the physical structure and the inherent properties, reliability of the dual damascene structure deteriorates. As a result, devices with such a dual damascene structure cannot perform normally.
U.S. Patent Publication No. 2001/00023333 (Huang) shows a method of fabricating a dual damascene structure. In this application, a barrier layer serves as an activation center for selective deposition during the selective deposition of the conductive layer. In contrast, a diffusion barrier layer does not serve as an active center. Accordingly, a high selectivity between the barrier layer and the diffusion barrier layer can be obtained.
U.S. Patent Publication No. 2003/0207564 (Ahn) shows a copper damascene structure. The structure includes a Ti-silicon-nitride barrier layer formed by organic-metallic atomic layer deposition. Copper is selectively deposited by a chemical vapor deposition (CVD) process and/or by an electrodeless deposition technique.
None of these applications address the problem described above.